1. Field of the Invention
The present invention relates generally to semiconductor electronics and more specifically to a device and method for the programming of a Flash-EPROM (erasable programmable read-only memories) type memory.
2. Description of Related Art
In Flash-EPROM memories, each information storage element or memory cell consists of a floating-gate MOS (metal oxide semiconductor) transistor that may be in one of two states. Thus, in the case of an N channel MOS transistor, in a first state called an erased state, no negative charge, or even a positive charge, is trapped at the floating gate. A conduction channel can then exist between the source and drain of this transistor. In a second state, called a programmed state, electrons are trapped in the floating gate. The electronics therefore prevent the creation of a conduction channel in the substrate between the source and drain. In this case, the transistor is off and behaves like an open circuit.
In a Flash-EPROM type memory, the passage of an electron from the conduction channel to the floating gate is done by a so-called hot electron method. To this end, high voltages are applied between the control gate and the drain of this same floating-gate transistor while the source is connected to the ground. These voltages enable the passage of very high-energy electrons (hot electrons), coming from the channel thus created, to the floating gate. The electrons are then trapped in the floating gate and constitute an information element. The removal of the charges, or erasure, is prompted by a tunnel effect.
A memory array consists of words comprising, in one example, at least eight cells each capable of containing an information element (namely one of the two previous states). FIG. 1 gives a partial view of an architecture of this kind. These cells may be selected individually. They are arranged in rows and columns.
In a standard architecture, all the floating-gate transistors of the memory cells of one word, or one byte in the example, have their control gates connected to the same voltage source by a word line and their sources connected to the same terminal of a selection transistor. This selection transistor permits or does not permit the biasing of the source of the floating-gate transistors of the word. An architecture of this kind with a selection transistor of this kind is described in the patent application EP-A-0 704 851. The selection transistor prevents the depletion of the floating-gate transistor of a cell and thus provides for perfect uniformity of the threshold voltage of the cells that are the object of an erasure.
This same selection transistor has its other electrode, namely its drain or source electrode, connected to a source vertical connection of words that are vertically adjacent. The vertically adjacent words are therefore on different rows. This selection transistor enables the biasing or non-biasing of the common sources of the floating-gate transistors of one word. These words have Q bytes. If Q=1, the word has one byte. The floating gates of the floating-gate transistors of the cells of the words in one row are connected to the same word line. Furthermore, the control gates of the selection transistors of the words of one row are connected to the same word selection line receiving an associated selection signal that is often identical to the signal applied to the word line.
With an architecture of this kind, there are constraints that limit the programming of several memory cells of one word during a programming cycle. Indeed, during the programming operation, the control gate of each cell of a row is subjected to a high voltage. The drain of the floating-gate transistor of a cell that is selected to be programmed is taken to a high voltage that is high enough to accelerate the charges in a channel. The source of this floating-gate transistor is taken to the ground. This high voltage enables the charges to acquire high energy, and produces a high current through this channel (500 .mu.A/cell). Thus, for one byte, the current produced during this programming may be in the range of 10 mA. This current is far too high for the vertical connection of the source which is limited in size and thus cannot withstand a current of such strength. For example, if many cells were to be programmed in the same word, the current produced would prompt a liberation of the metal film from the source vertical connection by a phenomenon of electromigration. Furthermore, this current which thereby prompts an elevation of the source current reduces the efficiency of the programming.
Accordingly, a need exists for a device and method for programming of a memory that overcomes this.